1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly a semiconductor device including a power supply voltage generating unit.
2. Description of the Related Art
A power supply voltage generating unit is conventionally known in "A Precise On-Chip Voltage Generator for a Giga-Scale DRAM with a Negative Word-line Scheme" (1998 Symposium on VLSI Circuits Digest of Technical Papers, pp. 94 to 95) by Hitoshi Tanaka et al.
In Japanese Laid Open Patent application (JP-A-Heisei 10-255469) is disclosed a circuit for generating a voltage higher than a power supply voltage externally supplied and a circuit for generating a negative voltage lower than a ground voltage. In this reference, the circuit is composed of a charge pump, two level detectors and two ring oscillators. The charge pump generates an internal power supply voltage higher than the external power supply voltage. The two level detectors detects the internal power supply voltage outputted from the charge pump. The two ring oscillators are respectively connected to the two level detectors and has different oscillation frequencies. A multiple ring oscillator selectively outputs to the charge pump, the signal generated by one of the ring oscillators in accordance with the internal power supply voltage which is outputted from the charge pump.
Also, the following matters are disclosed in the above reference. A MOS-type semiconductor integrated circuit at present includes a boosting circuit, which generates the internal power supply voltage higher than the power supply voltage externally supplied. The internal power supply voltage is supplied to the inside of the semiconductor integrated circuit such that a high level signal can be propagated without decrease, even if N-type MOSFETs are used. Also, a junction capacitance of a drain node is decreased so as to accomplish a high-speed operation and small power consumption. Also, the change of a threshold voltage due to the substrate effect is reduced to extend an operation margin. For these purposes, a power supply circuit system is provided to generate the internal voltage which is lower than the ground voltage externally supplied and to supply the inside of the semiconductor integrated circuit. At this time, the above power supply circuit system is requested to detect the change of the internal voltage due to operation current and leak current, and to hold the internal voltage such that the semiconductor integrated circuit is held in the normal operation.
It should be noted that various types of current flow such as the leak current equal to or less than 100 nA which is caused through the deviation in a manufacturing process and the semiconductor physics in a stand-by state, and the operation current of order of 10 .mu.A which is caused by the circuit structure for bias current. Considering the various types of current which extend over 5 digits, the internal voltage changes.
A conventional power supply voltage generating unit will be described with reference to FIGS. 1 and 2.
FIG. 1 shows the circuit structure of the power supply voltage generating unit for generating a negative voltage. The power supply voltage generating unit 10 is composed of a charge pump circuit CP, an oscillator OSC, a charge pump regulator Ha, an N-channel output transistor NH1, and a regulator H. The charge pump circuit CP is connected with a V.sub.BB voltage. The oscillator OSC is connected with the charge pump circuit CP. The charge pump regulator Ha has a voltage detecting circuit (level detector) Ld. The N-channel output transistor NH1 has the drain and source connected with the V.sub.BB voltage and a V.sub.NN voltage, respectively. The regulator H compares the V.sub.NN voltage with a reference value V.sub.REFN and outputs the comparing result to the gate of the output transistor NH1. The V.sub.BB voltage is a negative voltage of a substrate (Sub) voltage. The V.sub.NN voltage is a negative voltage which is connected with a circuit group (not shown) and is used in the operation of the circuit group. The V.sub.BB voltage and the V.sub.NN voltage are in the relation of V.sub.BB &lt;V.sub.NN.
When the circuit group connected with the side of V.sub.NN voltage operates, noise is generated so that the V.sub.NN voltage sometimes changes. For example, the noise contained on the side of V.sub.NN voltage has the amplitude of hundreds of mV. A load capacitance of thousands of pF is added to the side of V.sub.NN voltage and a load capacitance of hundreds of thousands of pF is added to the side of V.sub.BB voltage.
The operation of power supply voltage generating unit 10 will be described with reference to FIG. 2.
First, as shown in waveform A, the V.sub.NN voltage increases when the circuit group operates to introduce the noise. When a determination time t.sub.DET1 passes after the V.sub.NN voltage to start to increase, the regulator H operates as shown in waveform A as "regulator act" to output a high level signal of Vcc as an output signal H3 as shown in FIG. 42C.
When the H3 signal of the high level is supplied to the gate of the output transistor NH1, the output transistor NH1 is set to a conductive state. As a result, current flows from the side of V.sub.NN voltage to the side of V.sub.BB voltage to increase the V.sub.BB voltage as shown in waveform B. The noise on the side of V.sub.BB voltage, i.e., the V.sub.BB voltage noise shown in waveform B has the amplitude of tens of mV. While the output transistor NH1 is turned on, the current flows from the side of V.sub.NN voltage to the side of V.sub.BB voltage. Therefore, the noise contained on the side of V.sub.NN voltage decreases, and finally, the V.sub.NN voltage decreases and returns to the original level, as shown in waveform A.
The H3 signal goes to a low level of the V.sub.BB voltage to turn off the output transistor NH1, when the noise contained on the side of V.sub.NN voltage decreases so that the V.sub.NN voltage decreases lower than a predetermined voltage, as shown in waveform C. At this time, the V.sub.NN voltage is in a stable state as shown in waveform A. In this case, the side of V.sub.BB voltage is in the state in which the V.sub.BB voltage noise is contained. After a time t.sub.DET2 passes after the output transistor NH1 is turned on and the noise flows to the side of V.sub.BB voltage, as shown in waveform C, the output signal Hi of the level detector Ld becomes high level, as shown in waveform D. When the signal H1 becomes high level, the operation of the oscillator OSC is started, as shown in waveform E.
The charge pump circuit CP operates in response to the output signal H2 from the oscillator OSC (charge pump act shown in waveform E), the charge pump circuit CP removes the V.sub.BB voltage noise to decrease the V.sub.BB voltage, as shown in waveform B. When the V.sub.BB voltage falls lower than a preset voltage, the output signal H1 of the level detector Ld becomes the low level, as shown in waveform B. As a result, the operation of the oscillator OSC and the operation of the charge pump circuit CP are stopped as shown in waveform E.
By the way, when noise is contained on the side of V.sub.BB voltage and the V.sub.BB voltage as a substrate voltage changes from a predetermined value, the threshold voltage Vt of the transistor formed on the substrate changes so that the margin sometimes reduces. Therefore, it is desirable that a quantity of the V.sub.BB voltage noise transferred when the output transistor NH1 is set to the conductive state is small. Also, it is desirable that an attenuation time td is short from when the noise moves from the side of V.sub.NN voltage to the side of V.sub.BB voltage to when the V.sub.BB voltage noise is eliminated, as shown in waveform B.
In above-mentioned structure, the V.sub.BB voltage noise starts to be removed after the noise is contained on the side of V.sub.NN voltage and then the determination time t.sub.DET1 and the detection time t.sub.DET2 of the level detector Ld have elapsed. Here, the determination time t.sub.DET1 is 10 nsec, and the detection time t.sub.DET2 is 1 .mu.sec, for example.
Also, when the V.sub.BB voltage level is near the V.sub.NN voltage, the level change on the side of V.sub.BB voltage becomes late so that the noise produced on the side of V.sub.NN voltage does not attenuate immediately. This is because the operation of the charge pump circuit CP is started after the change of the voltage level on the side of V.sub.BB voltage, when the noise is generated on the side of V.sub.NN voltage.
FIG. 3 shows the circuit structure of the power supply voltage generating unit for generating a boosted voltage. In the power supply voltage generating unit 10A, a charge pump circuit CP is connected with a V.sub.pp voltage. The V.sub.pp voltage is a positive boosted voltage. A V.sub.CH voltage is the boosted voltage connected with a circuit group (not shown) and used for the operation of the circuit group. The V.sub.pp voltage and the V.sub.CH voltage are in the relation of V.sub.PP &gt;V.sub.CH.
The power supply voltage generating unit 10A is the same in structure as the power supply voltage generating unit 10 shown in FIG. 1, and different from that in polarity. As shown in FIG. 4, the operation of the power supply voltage generating unit 10A is substantially the same as that of the power supply voltage generating unit 10. The charge pump circuit CP operates to recover the V.sub.PP voltage to the original boosted voltage, when the noise generated on the side of V.sub.CH decreases V.sub.PP voltage to a predetermined value or below through a P-channel output transistor PG1.